With the coming of Ultra Large Scale Integrated (ULSI) DRAM devices, the sizes of memory cells have gotten smaller and smaller such that the area available for a single memory cell has become very small. This causes reduction in capacitor area, resulting in the reduction of cell capacitance. Accordingly, for the memory cells in DRAM devices, the most important issue currently is how to promote the storage ability and operation stability of capacitors when the scales of devices still decreases and the integration increases. Thus, the susceptibility of capacitors due to .alpha. particle radiation and soft errors is lowered, and the increasing refresh frequency is improved.
For solving the issues above, the prior art approaches to overcome these problems have resulted in the development of the various types of capacitors, such as the trench capacitor and the stacked capacitor. However, the manufacture of the stacked capacitor causes difficulties due to the limitation of the lithography technique. Besides, enormous stacked structures for promoting storage capacity usually cause the crack of the stacked structure occurring due to the unequally stress. On the other hand, the storing capacity of trench capacitor can not be promoted effectively due to the scale of trench capacitor is restricted. In additional, the tunneling leakage is also an important issue for manufacturing the trench capacitors with the scale of trench capacitor smaller than micrometer.
In general, the structure of the typical trench capacitors is illustrated in FIG. 1. First, the trench structures are formed in the substrate 2 by performing the etching step. Then, the doped areas 14 which acts as the first electrodes of the capacitors are formed in the lower sidewalls and bottoms of the trench structures in the substrate 2 by performing the impurity diffusion procedure. Next, the first conducting layer 18, the second conducting layer 22 and the amorphous layer 24 are formed in the trench structures to serve as the second electrodes of the trench capacitors. The capacitor dielectric films 16 are formed between the first conducting layer 18 and the doped areas 14 above for serving as a dielectric layer of the capacitor. Similarly, the collar oxide layer 20 is used to separate the second conducting layer 22 from the substrate 2. Besides, the amorphous layer 24 is electrically connected to the source/drain areas 30 of the transistor 28 to perform the required operation. And the shallow trench insulators (STI) 26 are formed on the amorphous layer 24 to separate the amorphous layer 24 and transistor devices 28.
It is noted that the second conducting layer 22, the drains of the transistor devices 28 and buried N-well 33, as shown in FIG. 1, constitute a vertical transistor. The second conducting layer 22 acts as the gate of the vertical transistor, and the drains 30 and the buried N-well 33 are used to serve as the source/drain areas of the vertical transistor respectively. And the collar oxide layer 20 acts as a gate oxide. Referring to FIG. 1, wherein a portion of the upper sidewalls of the trenches acts as the channel of the vertical transistor. But in actual operation, the collar oxide layer 20 is maintained at a consistent value to prevent the leakage currents ascribed to the vertical device. Especially the leakage current issues are more frequently because the potential level of the second conducting layer 22 for serving as the gate of the vertical transistor is higher through the transistors 28 to a higher voltage V.sub.cc. Thus for solving the leakage issues, the length of the collar oxide layer 20 is maintained to prevent forming the channels of the vertical devices for reducing the current leakage. Namely, the length of collar oxide layer 20 must be bigger than the predetermined limitation for defining the channel of the vertical transistor.
However, due to the length of the collar oxide layer 20 is limited by the design rules of the process window resulting that the trenches with higher aspect ratio can't used for the capacitors, the methods of increasing the depth of the trench structures are used to increase the surface areas of the doped areas 14 and to increase the capacitance. But with the increasing integration, the sizes of the trench structures are reduced mainly, and that causes the much difficulty happen in etching the trench to a enough predetermined depth, depositing the films and contacting layers into the trench structures for defining the various devices.